• DocumentCode
    416016
  • Title

    Pb-free bumping for high-performance SoCs

  • Author

    Ezawa, Hirokazu ; Seto, Msaharu ; Katsumata, Hiroshi

  • Author_Institution
    Adv. ULSI Process Eng. Dept., Toshiba Corp. Semicond. Co., Yokohama, Japan
  • Volume
    1
  • fYear
    2004
  • fDate
    1-4 June 2004
  • Firstpage
    655
  • Abstract
    We have already developed the eutectic Sn-Ag solder bumping process by alloying Ag/Sn electroplated metal stacks. Alloying electroplated Ag/Cu/Sn stacks has been also a successful process for Sn-Ag-Cu ternary alloy solder bumps, confirmed by characterizing melting temperatures and crystallographic phases. For high-performance system-on-chips (SoCs), the reliability problem of flip chip solder joints is extending from thermal fatigue failure to electromigration failure. As the dimensions of solder bumps shrink, the effects of voids in bumps and crystallographic texture of solder alloys on electromigration resistance must be discussed as well as current crowding. In this work, degassing from Ag/Sn stack-plated bumps has been investigated by thermogravimetry-gas-chromatography/mass-spectrometry (TG-GC/MS). In addition, the texture of electroplated Ag/Sn metal stacks after reflow under different cooling conditions has been characterized by electron backscatter diffraction (EBSD). The experimental results of the gas analyses suggest that the stack-plating process has potentially an advantage of reduction of voids in bumps because of the small amounts of evolved gases from the stacks-plated bumps in comparison with the alloy-plated bumps. From the EBSD results, the Ag/Sn stack as plated has highly [110] oriented β-Sn grains nearly parallel to the substrate surface. Under the reflow condition with a cooling rate of 200°C/min, the fraction of [110] oriented grains at around 50° angular tilts toward the substrate increases. As the cooling rate of the reflow process is reduced to 50°C/min, the strength of the closest-packed [100] texture of β-Sn parallel to the substrate surface increases.
  • Keywords
    chromatography; cooling; electromigration; electron backscattering; electron diffraction; electroplating; failure analysis; integrated circuit interconnections; integrated circuit metallisation; integrated circuit packaging; integrated circuit reliability; interface structure; mass spectroscopic chemical analysis; microassembling; reflow soldering; system-on-chip; thermal analysis; voids (solid); Ag-Sn; Ag/Sn electroplated metal stack alloying; Ag/Sn stack-plated bump degassing; EBSD; Pb-free bumping; Sn-Ag-Cu; Sn-Ag-Cu ternary alloy solder bumps; SnAg; SnAgCu; TG-GC/MS; alloy-plated bumps; cooling conditions; crystallographic phases; crystallographic texture; current crowding; electromigration failure; electromigration resistance; electron backscatter diffraction; electroplated Ag/Cu/Sn stack alloying; eutectic Sn-Ag solder bumping process; flip chip solder joint reliability; gas analysis; high-performance SoC; highly [110] oriented β-Sn grains; melting temperatures; metal stack reflow; solder bump dimensions; stack-plating process; stacks-plated bumps; system-on-chip; thermal fatigue failure; thermogravimetry-gas-chromatography/mass-spectrometry; voids; Alloying; Cooling; Copper alloys; Crystallography; Electromigration; Fatigue; Flip chip solder joints; System-on-a-chip; Temperature; Tin;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference, 2004. Proceedings. 54th
  • Print_ISBN
    0-7803-8365-6
  • Type

    conf

  • DOI
    10.1109/ECTC.2004.1319408
  • Filename
    1319408