DocumentCode :
416031
Title :
Near void free hybrid no-flow underfill flip chip process technology
Author :
Colella, Michael ; Baldwin, Daniel
Author_Institution :
AdAPT Lab., Georgia Inst. of Technol., Atlanta, GA, USA
Volume :
1
fYear :
2004
fDate :
1-4 June 2004
Firstpage :
780
Abstract :
This paper presents a systematic development of optimal no flow process underfill parameters compatible with four commercially available fluxing underfills. A novel hybrid process was developed that combines a capillary flow dynamic with no-flow fluxing underfills. The impact of the dispensing pattern on void formation is determined. Experiments are conducted to investigate the dispense pattern, placement speed and the impact of the placement process on interconnect yield further investigating the dispense pattern, placement force, and dwell time. A dispensed line pattern location and chip placement study is conducted to determine how voiding is affected by the position of the dispensed line in relation to the side of the die. The results of these experimental studies are used to select an optimal placement process for the materials. Reflow profile parameters are investigated using a parametric approach. The results of these initial studies are used to choose an optimal process for the materials. Test boards are assembled according to the optimal process for each material, and air to air thermal cycle, AATC, thermal cycling test is performed to qualify the assemblies. The newly developed edge patterned hybrid no-flow process has resulted in near void-free assemblies capable of passing 2000 cycles without an electrical failure for the -40 to 125°C AATC reliability test.
Keywords :
assembling; circuit reliability; encapsulation; flip-chip devices; integrated circuit packaging; reflow soldering; thermal stresses; voids (solid); -40 to 125 degC; AATC reliability test; board assembly; capillary flow dynamic; chip placement force; dispensed line pattern location; dispensing pattern; flip chip process technology; fluxing underfills; hybrid no-flow underfill; interconnect yield; near void free underfill; placement dwell time; placement process; placement speed; reflow profile; thermal cycling; void formation; Assembly systems; Conducting materials; Electronic packaging thermal management; Flip chip; Integrated circuit interconnections; Laboratories; Materials testing; Mechanical engineering; Performance evaluation; Vehicles;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference, 2004. Proceedings. 54th
Print_ISBN :
0-7803-8365-6
Type :
conf
DOI :
10.1109/ECTC.2004.1319426
Filename :
1319426
Link To Document :
بازگشت