Design and process optimization for reliable resistor pack solder joints for microprocessor packages

The integration of several passives into a single component is essential to keep them in the vicinity of the microprocessor, and their reliability becomes critical for the overall robustness of the product. This paper uses both modeling and experimental approaches to address design/process optimization for a resistor pack (R-pack, also known as chip resistor array) that has 4 resistors with 8 terminations integrated into one component. An array poses different challenges in design and assembly as pad spacing, pad length and fillet geometry need to be optimized for manufacturability and reliability. The effect of standoff height underneath the component and fillet is evaluated through modeling. It was found that the fillet has a significant impact on the overall reliability of the R-pack. Process parameters studied are: (a) effect of reflow conditions, especially cooling rate; (b) number of reflows; and (c) tilt. The reflow profile is the most important process parameter impacting the R-pack fatigue life since it affects the initial microstructure of the solder.