• DocumentCode
    416203
  • Title

    Fast and flexible buffer trees that navigate the physical layout environment

  • Author

    Alpert, C.J. ; Hrkic, M. ; Jiang Hu ; Quay, S.T.

  • Author_Institution
    IBM Corp., Austin, Texas
  • fYear
    2004
  • fDate
    7-11 July 2004
  • Firstpage
    24
  • Lastpage
    29
  • Abstract
    Buffer insertion is an increasingly critical optimization for achieving timing closure, and the number of buffers required increases significantly with technology migration. It is imperative for an automated buffer insertion algorithm to be able to efficiently optimize tens of thousands of nets. One must also be able to effectively navigate the existing layout, including handling large blockages, blockages with holes specifically for buffers, specially allocated buffer blocks, placement porosity, and routing congestion. The algorithm must also be flexible enough to know when to use and when not to use expensive layout resources. Although several previous works have addressed buffer insertion in the presence of blockages, this is the first to present a complete solution that can manage the physical layout environment.
  • Keywords
    Design engineering; Environmental management; Integrated circuit interconnections; Integrated circuit synthesis; Navigation; Permission; Repeaters; Routing; Space technology; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2004. Proceedings. 41st
  • Conference_Location
    San Diego, CA, USA
  • ISSN
    0738-100X
  • Print_ISBN
    1-51183-828-8
  • Type

    conf

  • Filename
    1322431