DocumentCode
416205
Title
Industrial experience with test generation languages gar processor verification
Author
Behm, M. ; Ludden, J. ; Lichtenstein, Y. ; Rimon, M. ; Vinov, M.
Author_Institution
IBM Development Center, Austin, Texas
fYear
2004
fDate
7-11 July 2004
Firstpage
36
Lastpage
40
Abstract
We report on our experience with a new test generation language for processor verification. The verification of two superscalar multiprocessors is described and we show the ease of expressing complex verification tasks. The cost and benefit are demonstrated: training takes up to six months; the simulation time required for a desired level of coverage has decreased by a factor of twenty; the number of escape bugs has ken reduced.
Keywords
Computer bugs; Graphical user interfaces; Hardware; Laboratories; Logic design; Permission; Power engineering and energy; Silicon; Testing; Time to market;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2004. Proceedings. 41st
Conference_Location
San Diego, CA, USA
ISSN
0738-100X
Print_ISBN
1-51183-828-8
Type
conf
Filename
1322433
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