Coding for systern-on-chip networks: a unified framework

In this paper, we present a coding framework derived from a communication-theoretic view of a DSM bus to jointly address power, delay, and reliability. In this framework, the data is first passed through a nonlinear source coder that reduces self and coupling transition activity and imposes a constraint on the peak coupling transitions on the bus. Next, a linear error control coder adds redundancy to enable error detection and correction. The framework is employed to efficiently conibine existing codes and to derive novel, codes that span a wide range of trade-offs between bus delay, codec latency, power, area, and reliability, Simulation results, for a l-cm 32-hit bus in a 0.18-μm CMOS technology, show that 31% reduction in energy and 62% reduction in enkrgy-delay product are achievable.