Title :
Re-synthesis for delay variation tolerance
Author :
Chang, Shih-Chieh ; Hsieh, Cheng-Tao ; Wu, Kai-Chiang
Author_Institution :
National Tsing Hua University, Taiwan
Keywords :
Artificial intelligence; Circuit noise; Circuit optimization; Degradation; Delay; Logic; Permission; Protection; Timing; Wires;
Conference_Titel :
Design Automation Conference, 2004. Proceedings. 41st
Conference_Location :
San Diego, CA, USA
Print_ISBN :
1-51183-828-8
