DocumentCode
416348
Title
Post-layout logic optimization of domino circuits
Author
Cao, Aiqun ; Koh, Cheng-Kok
Author_Institution
Purdue University, West Lafayette, IN
fYear
2004
fDate
7-11 July 2004
Firstpage
820
Lastpage
825
Keywords
Algorithm design and analysis; CMOS logic circuits; Circuit synthesis; Costs; Delay; Integrated circuit synthesis; Logic circuits; Logic design; Pulse inverters; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2004. Proceedings. 41st
Conference_Location
San Diego, CA, USA
ISSN
0738-100X
Print_ISBN
1-51183-828-8
Type
conf
Filename
1322595
Link To Document