High-PSR bias circuitry for NTSC sync separation

Author

Wang, Chua-Chin ; Tseng, Yih-Long ; Lee, Tzung-Je ; Hu, Ron

Author_Institution

Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

Volume

1

fYear

2004

fDate

23-26 May 2004

Abstract

This paper presents a simple and bias generation circuitry (BGC) with temperature compensation. The proposed BGC utilizes step-down regulators and a bandgap-based bias with cascade current control. The clamping voltages required for sync separation from an NTSC signal are generated. Detailed PSR (power rejection ratio) analysis of the proposed BGC is also derived to circumscribe the clamping voltage variation. The worst variation of the proposed design verified by HSPICE post-layout simulations is 4.2% given a [-50°C, +150°C] temperature range, and a VDD(=5V) +10%.

Keywords

SPICE; circuit simulation; compensation; power supply circuits; video coding; voltage regulators; -50 to 150 C; 5 V; HSPICE; NTSC signal; NTSC sync separation; bandgap-based bias; bias generation circuitry; cascade current control; clamping voltage variation; high-PSR bias circuitry; layout simulations; power rejection ratio; step-down regulators; temperature compensation; Circuits; Clamps; Clocks; Operational amplifiers; Photonic band gap; Power supplies; Regulators; Signal generators; Temperature; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1328198

Filename

1328198