A 1-V 400MS/s 14bit self-calibrated CMOS DAC with enhanced dynamic linearity

Author

Saeedi, S. ; Mehrmanesh, S. ; Atarodi, M. ; Aslanzadeh, H.A.

Author_Institution

Sharif Univ. of Technol., Tehran, Iran

Volume

1

fYear

2004

fDate

23-26 May 2004

Abstract

A 1-V CMOS current steering digital to analog converter with enhanced static and dynamic linearity is presented. The 14-bit static linearity is achieved by a background analog self calibration technique which is suitable for low voltage applications and does not require error measurement and correction circuits. The improved dynamic linearity at high frequencies, a low power track/attenuate output stage is used at the DAC output. Integral and differential nonlinearities of the proposed DAC corresponding to a 14-bit specification are less than 0.35LSB and 0.25LSB, respectively. The DAC is functional up to 400MS/s with SFDR better than 71dB in the Nyquist band. The circuit has been designed and simulated in a standard 0.18μm CMOS technology.

Keywords

CMOS integrated circuits; calibration; digital-analogue conversion; nonlinear dynamical systems; 0.18 microns; 1 V; 14 bit; CMOS DAC; CMOS technology; Nyquist band; SFDR; attenuate output stage; background analog self calibration; current steering DAC; differential nonlinearities; enhanced dynamic linearity; enhanced static linearity; error correction circuits; error measurement; integral nonlinearities; low voltage applications; self-calibrated CMOS; track output stage; CMOS technology; Calibration; Circuit simulation; Decoding; Digital-analog conversion; Error correction; Frequency; Linearity; Low voltage; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1328203

Filename

1328203