A 1.5 V high-linearity CMOS mixer for 2.4 GHz applications

Author

Wei, Hung-Che ; Weng, Ro-Min ; Lin, Kun-Yi

Author_Institution

Dept. of Electr. Eng., National Dong Hwa Univ., Hualien, Taiwan

Volume

1

fYear

2004

fDate

23-26 May 2004

Abstract

A folded-cascode mixer with a modified class-AB transconductor for 2.4 GHz ISM band applications is presented in this paper. The mixer is composed of a modified class-AB transconductor and a low-voltage design technique. The proposed architecture improves the performance of linearity in the RF front-end. Simulation results for the proposed mixer using TSMC 0.8 μm mixed signal CMOS process are: input 1-dB compression point (P -1dB) -1.15 dBm, input third-order intercept point (IIP3) 11 dBm, power conversion gain 1 dB, and single side-band noise figure 17.3 dB. The mixer consumes 5.86 mA of current from a 1.5 V power supply.

Keywords

CMOS integrated circuits; low-power electronics; mixed analogue-digital integrated circuits; mixers (circuits); operational amplifiers; 0.8 micron; 1 dB; 1.5 V; 17.3 dB; 2.4 GHz; 5.86 mA; RF front-end; TSMC mixed signal CMOS process; class-AB transconductor; folded-cascode mixer; high-linearity CMOS mixer; input third-order intercept point; linearity performance; low-voltage mixer design; Bluetooth; CMOS process; CMOS technology; Circuits; Linearity; Mixers; Noise figure; Radio frequency; Transconductors; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1328256

Filename

1328256