An improved algorithmic ADC clocking scheme

Author

Kim, Min Gyu ; Ahn, Gil-Cho ; Moon, Un-Ku

Author_Institution

Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR, USA

Volume

1

fYear

2004

fDate

23-26 May 2004

Abstract

An improved algorithmic ADC clocking scheme is presented. Using an optimized clock generator, a significant improvement in conversion speed is achieved in the converter. This proposed optimized clock generator removes the wasted time which exists during all conversion cycles except for the first one. This technique can improve the conversion speed up to 82% compared to conventional algorithmic ADCs. Alternatively, static power consumption can also be reduced for a given conversion speed. An algorithmic ADC using the new clocking scheme is validated using MATLAB behavioral simulations.

Keywords

analogue-digital conversion; circuit optimisation; circuit simulation; clocks; convertors; MATLAB behavioral simulation; algorithmic ADC clocking scheme; conversion cycle; conversion speed improvement; converter; optimized clock generator; static power consumption reduction; wasted time removal; Algorithm design and analysis; Bandwidth; Clocks; Computer science; Digital-analog conversion; Energy consumption; MATLAB; Moon; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1328263

Filename

1328263