• DocumentCode
    418054
  • Title

    An input-free NMOS VT extractor circuit in presence of body effects

  • Author

    Sengupta, S.

  • Author_Institution
    Sch. of ECE, Georgia Inst. of Technol., Atlanta, GA, USA
  • Volume
    1
  • fYear
    2004
  • fDate
    23-26 May 2004
  • Abstract
    An input-free NMOS VT (threshold voltage) extractor circuit in an n-well CMOS process is presented. The non-idealities due to NMOS body effects on the extracted VT are automatically compensated in the circuit. PMOS difference amplifiers are developed to compute the difference of node voltages such that the VT of the NMOS device can be extracted as a voltage, referenced to ground or VDD. The proposed NMOS V2 extractor circuit was fabricated in a 0.25 μm CMOS process, and the extracted VT, which had an absolute value of 0.441V, had an accuracy of 95.7%.
  • Keywords
    CMOS integrated circuits; MOSFET; differential amplifiers; 0.25 micron; 0.441 V; NMOS device; NMOS extractor circuit; PMOS difference amplifiers; body effects; n-well CMOS process; node voltages; threshold voltage; CMOS process; CMOS technology; Circuits; Curve fitting; Data mining; MOS devices; Monitoring; TV; Temperature sensors; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
  • Print_ISBN
    0-7803-8251-X
  • Type

    conf

  • DOI
    10.1109/ISCAS.2004.1328344
  • Filename
    1328344
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=418054