An SoC compatible linearity test approach for precision ADCs using easy-to-generate sinusoidal stimuli

Analog and mixed-signal test is identified as one of the most daunting challenges for system-on-a-chip design. The bottleneck of mixed-signal test is the instrumentation of high precision signal generators and response measurement devices. This paper provides a cost-effective solution to the mixed-signal stimuli instead of accurate signals generated by very expensive testers. We take the ADC linearity test as a vehicle to study the performance of the proposed approach. A low-linearity sine wave and an attenuated copy of the sine-wave are used in the histogram test for an ADC. A stimulus error identification and removal algorithm is derived such that the ADC´s linearity can be accurately determined without being affected by the sine wave´s non-linearity. Simulation results show that 16-bit test accuracy can be achieved by using sine waves with a 38-dB SFDR, corresponding to a 6-bit linearity. This approach is applicable to test fully differential ADCs and extendable to other mixed-signal functions of IC products.