Design of a pixel array circuit for thinning process

Author

Wang, Chunyan ; Wu, Kuo-Ting

Author_Institution

Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada

Volume

3

fYear

2004

fDate

23-26 May 2004

Abstract

In this paper, a pixel array circuit for image acquisition and thinning is presented. The circuit is designed to have a simple structure with four connections per pixel. In each pixel, the operations for the thinning process are performed using simple MOS switches and latches. Logic functions are implemented in NMOS pass transistor logic gates to minimize the circuit area and the power dissipation. The pixel array circuit can be implemented using a CMOS digital technology with a reasonable pixel density, which facilitates its integration in digital processing systems.

Keywords

CMOS image sensors; CMOS logic circuits; feature extraction; fingerprint identification; image thinning; CMOS digital technology; MOS switches; NMOS pass transistor logic gates; digital processing systems; image acquisition; latches; logic functions; pixel array circuit; pixel density; power dissipation; thinning process; CMOS logic circuits; CMOS technology; Latches; Logic circuits; Logic functions; Logic gates; MOS devices; Pixel; Power dissipation; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1328690

Filename

1328690