Improved cell core for a mixed-mode polynomial CNN

This paper proposes improvements for a recently reported mixed-mode polynomial CNN cell structure. Like the previous cell core, the improved cell can be used to process input data that has been divided into blocks (layers), while keeping all input/output operations during processing local. The improved cell core uses current memories as means to convey data between different blocks. This way only one DA converter and polynomial circuit is needed in the cell and the current sources of the DAC can also be utilized in the ADC. In addition to gray-scale processing, the cell is capable of processing binary data so that the eight-bit gray-scale state memory can be used as eight one-bit local memories. The analog circuits of the design are composed of simple primitives which make the design well suited for implementation using modern silicon process.