A low-power fractional decimator architecture for an IF-sampling dual-mode receiver

In this paper, a low-power fractional decimator architecture for a GSM/WCDMA dual-mode receiver is presented. The decimation by a fractional ratio is performed using a cascaded integrator-comb filter with three parallel derivator branches, and a linear interpolator. In the proposed design, all the integrators are clocked at half the sample rate, which is possible by utilizing the zero samples produced in the downconversion. Although the presented architecture has a larger layout area than the traditional designs, this maximum clock frequency reduction yields lower power consumption and, depending on the implementation technology and parameters, a possibility to use more power- and area-efficient adders in the speed-critical integrator section.