Effectiveness of energy recovery techniques in reducing on-chip power density in molecular nano-technologies

As scaling of silicon devices continues at an aggressive pace, the problems with it are becoming more and more evident. With ´short channel effects´ already in the way of scaling interest has shifted to the possible use of non-silicon molecular devices for circuit implementation. Carbon nanotube has emerged as a promising candidate. However, molecular devices such as carbon nanotube FETs (CNFETs) with their super-scaled dimensions and high current densities would increase the power density on chip and reasonable predictions estimate that they would far exceed the maximum power density limitation as stated in the ITRS (2001). This paper explores the use of energy-recovery techniques in molecular CNFET based digital circuits and demonstrates how they can solve the power density problem in such circuits.