DocumentCode
418236
Title
A data reusing architecture for MPEG video coding
Author
Moshnyaga, Vasily G. ; Masunaga, Koichi ; Kajiwara, Naoki
Author_Institution
Dept. of Electron. & Comput. Sci., Fukuoka Univ., Fokuoka, Japan
Volume
3
fYear
2004
fDate
23-26 May 2004
Abstract
This paper presents a new architecture capable of drastically reducing computations and memory accesses in MPEG video coding. The key idea is to reuse data stored in frame memory to disable memory re-writes and motion estimation computations for stationary macroblocks. Due to dynamic memory sharing among reference frames, data-driven macroblocks characterization and processing, the architecture reduces the number of frame memory writes and motion estimation operations by 85% while maintaining high picture quality.
Keywords
memory architecture; motion estimation; video coding; MPEG video coding; data reusing architecture; data-driven macroblocks; dynamic memory sharing; frame memory; memory accesses reductions; memory rewrites; motion estimation; picture quality; reference frames; stationary macroblocks; Computer architecture; Computer science; Encoding; Image reconstruction; Motion estimation; Read-write memory; Streaming media; Strips; Video coding; Video sharing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN
0-7803-8251-X
Type
conf
DOI
10.1109/ISCAS.2004.1328867
Filename
1328867
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