DocumentCode
418274
Title
Memory optimization techniques for UMTS code generation
Author
Iacono, Daniele Lo ; Messina, Ettore ; Avellone, Giuseppe ; Galluzzo, Agostino
Volume
4
fYear
2004
fDate
23-26 May 2004
Abstract
This paper presents a novel architecture for pseudo-noise (PN) sequences generation. We briefly review some theoretic aspects of the finite field arithmetic applied to the PN sequences generation, showing the most commonly used generator structures, and developing some techniques aimed at reducing the generators´ memory requirements. The proposed architecture, developed for the downlink UMTS-FDD mode, exhibits a considerable memory reduction as well as a limited hardware complexity if compared with a conventional generator, and hence is well fit for the Mobile Station (MS) integration.
Keywords
3G mobile communication; memory architecture; pseudonoise codes; spread spectrum communication; PN; UMTS code generation; downlink UMTS-FDD scrambling code generator architecture mode; frequency division duplex; hardware complexity; memory optimization method; memory reduction; mobile station integration; pseudonoise sequences generation; universal mobile telecommunication system; 3G mobile communication; Arithmetic; Bandwidth; DC generators; Downlink; Galois fields; Linear feedback shift registers; Multiaccess communication; Polynomials; State feedback;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN
0-7803-8251-X
Type
conf
DOI
10.1109/ISCAS.2004.1328943
Filename
1328943
Link To Document