Fast-switching analog PLL with finite-impulse response

Author

Levantino, S. ; Romano, L. ; Samori, C. ; Lacaita, A.L.

Author_Institution

Politecnico di Milano, Italy

Volume

4

fYear

2004

fDate

23-26 May 2004

Abstract

This paper proposes a method for speeding up the linear settling response of integer-N PLL´s. Extending the discrete-time model of the PLL, simple design rules are derived which guarantee accurate frequency settling in few reference cycles. Simulations show that the proposed technique can improve the settling time of a conventional PLL by about 10 times. A 2.5-GHz frequency synthesizer with 1-MHz reference is designed according to the proposed technique in an existing 0.35 μm-CMOS technology. A 60-MHz frequency step within 0.1-ppm accuracy is performed in 15 μs. The simulated reference spur is -60 dBc.

Keywords

CMOS analogue integrated circuits; circuit switching; discrete time systems; frequency convertors; frequency synthesizers; integrated circuit modelling; phase locked loops; transient response; 0.35 micron; 15 mus; 2.5 GHz; CMOS technology; accurate frequency settling; design rules; discrete time model; fast switching analog PLL; finite impulse response; frequency synthesizer; integer N PLL; linear settling response; reference cycles; simulated reference spur; Bandwidth; Channel spacing; Communication standards; Filters; Frequency synthesizers; Phase locked loops; Stability; Switches; Voltage-controlled oscillators; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1328966

Filename

1328966