DocumentCode :
418290
Title :
Reed-Solomon behavioral virtual component for communication systems
Author :
Casseau, E. ; Le Gal, B. ; Jego, C. ; Le Heno, N. ; Martin, E.
Author_Institution :
LESTER Lab., CNRS, France
Volume :
4
fYear :
2004
fDate :
23-26 May 2004
Abstract :
In this paper, we focus on the design of a communication system based on reusing IP cores. We consider that traditional methods for hardware design at the RT level suffer from heavy limitations that prevent them from efficiently addressing the algorithmic complexity and the high flexibility required by the various application profiles. We propose to raise the abstraction level of the specification and introduce the notion of architectural flexibility of an IP core by benefiting from the emerging high-level synthesis tools. Our method has been successfully applied to the design of a Reed-Solomon (RS) decoder IP core, targeting the DVB-DSNG digital video broadcasting standard. We are able to generate a variety of RS decoder architectures, with varying hardware complexity and computation speed, from a single behavioral-level VHDL specification.
Keywords :
Reed-Solomon codes; computational complexity; decoding; digital video broadcasting; hardware description languages; industrial property; IP cores; RT level; Reed-Solomon behavioral virtual component; Reed-Solomon decoder; VHDL specification; algorithmic complexity; architectural flexibility; communication systems; computation speed; digital video broadcasting; hardware complexity; hardware design; intellectual property cores; Algorithm design and analysis; Decoding; Design methodology; Digital video broadcasting; Hardware design languages; High level synthesis; Laboratories; Reed-Solomon codes; Synthetic aperture sonar; Time to market;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
0-7803-8251-X
Type :
conf
DOI :
10.1109/ISCAS.2004.1328968
Filename :
1328968
Link To Document :
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