Direct digital frequency synthesizer with multi-stage linear interpolation

Direct digital frequency synthesizers (DDFS´s) are playing an important role in modern communication systems. One of the problems of the DDFS is a phase-to-amplitude converter (PAC) based on ROM. The large size ROM yields not only better frequency resolution and better spurious performance, but also higher power consumption and lower speed. This papers proposes a new type of DDFS with a multi-stage interpolation scheme to convert the phase data into sinusoid amplitude. The multi-stage interpolation provides better approximation while the increase of the ROM size is held minimum. Better approximation ability of the proposed DDFS reduces the spurious performance. The simulation and experimental results show that it can achieve a considerable savings in the required ROM capacity while respectable spurious performance is provided.