A power constrained simultaneous noise and input matched low noise amplifier design technique

Author

Nguyen, Trung-Kien ; Su, Yang-Moon ; Lee, Sang-Gug

Author_Institution

Inf. & Commun. Univ., Daejeon, South Korea

Volume

4

fYear

2004

fDate

23-26 May 2004

Abstract

In this paper, very simple and insightful sets of noise parameters expressions for a power-constrained simultaneous noise and input matching (PCSNIM) CMOS LNA design technique are newly introduced. Based on the noise parameters expression, the design principle, advantages, and limitations are clearly explained. The proposed LNA is optimized for low voltage, low power 900 MHz Zigbee applications based on 0.25 μm CMOS technology. Measurement results show a power gain of 12 dB, NF and NF_min of 1.35 dB, and IIP3 of -4 dBm while dissipating the DC current of 1.6 mA (only 0.7 mA for NMOS transistor) at a supply voltage of 1.25 V.

Keywords

CMOS integrated circuits; integrated circuit design; integrated circuit noise; power amplifiers; 0.25 micron; 0.7 mA; 1.25 V; 1.35 dB; 1.6 mA; 12 dB; 900 MHz; CMOS LNA design; Zigbee applications; input matching; low noise amplifier design; noise parameters; power constrained simultaneous noise; CMOS technology; Current measurement; Gain measurement; Impedance matching; Low voltage; Low-noise amplifiers; MOSFETs; Noise measurement; Power measurement; ZigBee;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1328995

Filename

1328995