Modeling and diagnosis of analog circuits with probabilistic graphical models

We describe an algorithm to build a graphical model-more precisely: a join tree representation of a Markov network-for a steady state analog circuit. This model can be used to do probabilistic diagnosis based on manufacturer supplied information about nominal values of electrical components and their tolerances as well as measurements made on the circuit. Faulty components can be identified by looking for high probabilities for values of characteristic magnitudes that deviate considerably from the nominal values.