A scalable compact architecture for the computation of integer binary logarithms through linear approximation

This paper presents the realization of a scalable architecture, the Negative Logarithmic Function (NLF), for the integer calculation of nonlinear functions. It shows how to implement the desired analog logarithm and its reciprocal function with very little logic and a maximizable accuracy. After introducing the NLF module and its properties, we describe the way the continuous function is approached in order to come across the hardware realization. A simple solution is given to reduce the error made by the approximation, as well as the architecture for the reverse transformation. To illustrate the method, examples are given in which the width of the input value has been arbitrarily fixed to 8 bits, whereas the scalable architecture supports every kind of bus width.