Modulo deflation in (2n+1, 2n, 2n-1) converters

In this paper, a new modulo reduction theorem is introduced to decompose the base of the modulo operation. As one of possible applications, this new theorem can be used to further reduce the modulo size of the modified Chinese remainder theorem (CRT). Based on this new theorem, an improved modulo size reduced CRT algorithm for M={2ⁿ+1, 2ⁿ, 2ⁿ-1} is presented. For the most popular three-moduli set M, the design and FPGA implementation show that the proposed modulo part of the residue-to-binary(R/B) converter is almost twice faster and needs 50% less hardware and power than the modulo operation of the two converters previously published in the literature.