Substrate noise-aware floorplanning for mixed-signal SOCs

To reduce substrate-coupling noise in mixed-signal SOCs, we propose a new floorplanning method that considers substrate-coupling noise and adjusts placement of digital and analog blocks to reduce the influence of digital switching on the performance of sensitive analog circuits. A simple model of the influence of distance between blocks on distortion is used to compute a distortion number for a layout. As a result of noise optimization during floorplanning, the distortion numbers for MCNC benchmark-based circuits are significantly reduced compared to floorplans generated without optimizing for noise. Experimental results are very encouraging.