DocumentCode
418494
Title
Parameterized SoC design for portable systems
Author
Bhutoria, Sumant ; Chakrabarti, Chaitali
Author_Institution
Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA
Volume
2
fYear
2004
fDate
23-26 May 2004
Abstract
Portable devices have ushered in the use of parameterizable SoC architectures that provide flexibility and applicability while remaining cost-effective. Platune provides a mechanism for designing such architectures by exploring a large configuration space to arrive at pareto-optimal configurations with respect to power. In this paper, we argue that the pareto-optimal configurations for portable devices have to be derived for battery performance and not for power or energy consumption. We illustrate through examples that the optimal configuration obtained by optimizing battery performance is quite different from those obtained by optimizing power or energy.
Keywords
Pareto optimisation; circuit optimisation; system-on-chip; battery performance; cost-effective; large configuration space; optimizing energy; optimizing power; parameterizable SoC architecture; parameterized SoC design; pareto-optimal configuration; portable device; portable system; Batteries; Computer architecture; Design optimization; Electronics industry; Embedded system; Energy consumption; Low power electronics; Portable computers; Power system modeling; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN
0-7803-8251-X
Type
conf
DOI
10.1109/ISCAS.2004.1329305
Filename
1329305
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