An improved technique to increase noise-tolerance in dynamic digital circuits

Author

Mendoza-Hernandez, F. ; Linares, M. ; Champac, V.H.

Author_Institution

Dept. of Phys. Investigation, Sonora Univ., Mexico

Volume

2

fYear

2004

fDate

23-26 May 2004

Abstract

Due to the rapid scaling of the transistor and interconnect dimensions the VLSI circuit technology is having an impressive advancement. However, noise issues emerge as an important cost in deep submicron circuits. In this paper we propose an improved noise-tolerant dynamic digital circuit technique. By using a charge redistribution process together with the conventional precharge of internal nodes in logic gates, the noise immunity is increased. Simulation results show an improvement of up to 8.6×over conventional dynamic logic.

Keywords

CMOS integrated circuits; VLSI; digital circuits; integrated circuit noise; logic gates; CMOS circuit; VLSI circuit technology; charge redistribution process; charge transfer technique; complementary metal oxide semiconductor; deep submicron circuits; dynamic digital circuits; logic gates; noise tolerant technique; very large scale integration; CMOS logic circuits; Circuit noise; Circuit simulation; Crosstalk; Digital circuits; Integrated circuit interconnections; Logic gates; Transistors; Very large scale integration; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329315

Filename

1329315