An asynchronous SOVA decoder for wireless communication application

This paper presents a novel asynchronous architecture for a Soft-Output Viterbi Algorithm (SOVA) decoder. This architecture is based on two-step SOVA and asynchronous circuit design. Novel asynchronous traceback structure allows the majority of the data to be static in memory to reduce switching activity and power consumption. This architecture also minimizes the read-write operation of memory. We have designed an asynchronous architecture for SOVA decoder for low power wireless communication applications. This work shows an asynchronous implementation of SOVA decoder running at 2M symbol/s at 6.23 mW, which is suitable in wireless communication such as 3G handsets.