A new level restoration circuit for multi-valued logic

Author

Morgül, Avni ; Temel, Turgay

Author_Institution

Dept. of Electr. & Electron. Eng., Bogazici Univ., Istanbul, Turkey

Volume

2

fYear

2004

fDate

23-26 May 2004

Abstract

Compared to binary logic, the multi-valued logic circuits provide very small chip size, higher speed, and considerably small number of interconnections and simpler realization of logic functions. However, the main drawback of these circuits is the lower noise margin. The noise margin decreases as the radix of multi-valued system increases. Due to the low noise margins, it is necessary to restore or recover the nominal levels of the signal after a certain number of cascaded stages. In this paper a new current mode CMOS restoration circuit is presented and evaluated.

Keywords

CMOS logic circuits; high-speed integrated circuits; integrated circuit design; integrated circuit interconnections; integrated circuit noise; logic design; logic simulation; multivalued logic circuits; chip size; current mode CMOS restoration circuit; interconnections; logic functions; lower noise margin; multivalued logic circuit; Arithmetic; CMOS logic circuits; Circuit noise; Integrated circuit interconnections; Logic circuits; Logic functions; Multivalued logic; Noise level; Noise reduction; Signal restoration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329355

Filename

1329355