Title :
A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic
Author :
Yang, Ge ; Jung, Seong-Ook ; Baek, Kwang-Hyun ; Kim, Soo Hwan ; Kim, Suki ; Kang, Sung-Mo
Author_Institution :
Dept. of Electr. Eng., California Univ., Santa Cruz, CA, USA
Abstract :
We have developed Dual Path All-N-logic (DPANL) and applied to 32-bit adder design for higher performance. The speed enhancement is mainly due to reduced capacitance at each evaluation node of dynamic circuits. Post-layout simulation results show that this adder can operate at frequencies up to 1.85 GHz for 0.35 μm 1P4M CMOS technology and is 32.4% faster than the adder using all-N-transistor (ANT). It also consumes 29.2% less power than the ANT adder. A 0.35 μm CMOS chip has been fabricated and tested to verify the functionality and performance of the DPANL adder on silicon.
Keywords :
CMOS logic circuits; adders; integrated circuit modelling; integrated circuit testing; logic testing; power consumption; 0.35 micron; 1.85 GHz; 32-bit adder; CMOS chip; CMOS technology; Dual Path All-N-Logic; Si; all-N-transistor; capacitance; carry lookahead adder; dynamic circuits; evaluation node; post layout simulation; silicon; Adders; CMOS logic circuits; CMOS technology; Capacitance; Circuit simulation; Clocks; Feedback; Frequency; MOS devices; Voltage;
Conference_Titel :
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
0-7803-8251-X
DOI :
10.1109/ISCAS.2004.1329388
