Modeling and designing energy-delay optimized wide domino circuits

In this paper, we present simple analytical models for energy (switching+short circuit) per transition and delay for wide-NOR domino logic gates. These gates are used to design register files (RFs) in high performance microprocessors and priority encoders for content addressable memory (CAMs). They contribute significantly to the overall switching energy and read delay, therefore require accurate modeling and optimized designing. Our results for a 130 nm bulk CMOS technology indicate that the energy (delay) models track SPICE simulations to within 4% (7%) for a large range of load and delay conditions. The results show that, optimal energy-delay operation is a function of the number of pulldown paths. It is achieved when the wide-NOR gate equivalent fan-out is between 2.3-2.7.