Embedded computation of maximum-likelihood phylogeny inference using platform FPGA

Our previous work to accelerate phylogeny inference using HW/SW(hardware/software) co-design has recently been extended to a more powerful embedded computing platform. In this platform, a microprocessor is immersed into field programmable gate array (FPGA) fabric for realizing an effective environment for HW/SW co-design implementation. Significant improvements in data transmission between hardware and software and higher clock frequency of FPGA have been realized when compared to the JBits interface in the previous design. In addition, the embedded platform provides a greater flexibility in partitioning hardware and software tasks. These new features lead to much faster computation speed for phylogeny inference. In this paper, the architecture for HW/SW co-design in the embedded platform is presented. The FPGA logic design for the tree likelihood evaluation has also been improved to tackle problem of larger scale by adopting the idea of partial likelihood.