Microwave characterization of high aspect ratio through-wafer interconnect vias in silicon substrates

In this paper, we present detailed fabrication process and high-frequency characterization of through-wafer copper-filled via holes ranging from 40 μm to 70 μm in diameter on 400 μm-thick silicon substrates. The high aspect ratio via holes are achieved by carefully tuning the inductively coupled plasma (ICP) etching process and the high aspect ratio via holes are filled completely using a bottom-up electroplating approach. The fabricated via holes were characterized using different resonating structures and the measured inductance and resistance of the 70 μm via are 409 pH and 0.154Ω respectively. In addition, the effect of the via arrangement on the resulting inductance are also evaluated.