A partial reconfigurable architecture for controllers based on Petri nets

The digital control systems in industry has been used in most of the applications based on expensive programmable logical controllers (PLC). These systems are, in general, highly complex and slow, with an operation cycle around 10 ms. In this work, a reconfigurable logic controller (RLC) approach is presented, based on a small and low cost Xilinx Virtex-II FPGA architecture, operating as a virtual hardware machine. In this context, the main process is specified in a formal language, based on Petri nets or SFC (sequential function chart). For applications that demand more hardware than that available in the FPGA, a partial reconfiguration mechanism takes place. From the Petri net specification, the main process is split into multiple contexts, which are sequentially executed within the same FPGA, without violating the operation cycle of application.