Title :
Distributed arithmetic FPGA design with online scalable size and performance
Author_Institution :
Paderborn Univ., Germany
Abstract :
The partial runtime reconfiguration capability of FPGAs allows task execution in a multitasking manner. In contrasts to most other models, we assume that each task has several implementation variants with different performance and size. Moreover, one task variant is an extension of another. Therefore, a task can change between its variants without reconfiguring the entire task footprint. As case study, we introduce an online scalable distributed arithmetic design and review the advantages.
Keywords :
distributed arithmetic; field programmable gate arrays; integrated circuit design; multiprogramming; reconfigurable architectures; FPGA design; field programmable gate array; multitasking; online scalable distributed arithmetic design; partial runtime reconfiguration; task execution; Arithmetic; Coprocessors; Educational institutions; Field programmable gate arrays; Hardware; Microprocessors; Multitasking; Permission; Runtime; Signal processing;
Conference_Titel :
Integrated Circuits and Systems Design, 2004. SBCCI 2004. 17th Symposium on
Print_ISBN :
1-58113-947-0
DOI :
10.1109/SBCCI.2004.241293
