DocumentCode
423586
Title
Mapping LSSVM on digital hardware
Author
Anguita, Davide ; Boni, Andrea ; Zorat, Alessandro
Author_Institution
Dept. of Biophys. & Electron. Eng., Genoa Univ., Italy
Volume
1
fYear
2004
fDate
25-29 July 2004
Lastpage
571
Abstract
In this paper we show how to map a LSSVM on digital hardware. In particular, we provide a theoretical analysis of quantization effects, due to finite register lengths, that leads to some useful bounds for computing the necessary number of bits for a correct hardware implementation. Then, we describe a new FPGA-based architecture, the KTRON, which implements the feed-forward phase of a LSSVM.
Keywords
feedforward; field programmable gate arrays; least squares approximations; quantisation (signal); support vector machines; FPGA-based architecture; digital hardware; field programmable gate arrays; finite register lengths; quantization effects; Algorithm design and analysis; Communications technology; Computer architecture; Field programmable gate arrays; Hardware; Kernel; Quantization; Registers; Support vector machine classification; Support vector machines;
fLanguage
English
Publisher
ieee
Conference_Titel
Neural Networks, 2004. Proceedings. 2004 IEEE International Joint Conference on
ISSN
1098-7576
Print_ISBN
0-7803-8359-1
Type
conf
DOI
10.1109/IJCNN.2004.1379971
Filename
1379971
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