Modified lifting algorithm and VLSI architecture for the 9/7 wavelet filters

A new parallel-based lifting algorithm (PBLA) for the 9/7 filters, exploring the parallelism of arithmetic operations in each lifting step, was proposed in this paper. It shortened significantly the critical path of computation, and resulted in a fast VLSI implementation architecture. In comparison with the conventional lifting algorithm based implementation (CLABI), the latency is reduced by more than half from (4T_m + 8T_a) to (T_m + 4T_a), which is competitive to that of convolution based implementation CBI, and can be further reduced to Tm by inserting 3 stages of pipeline. The experimental results demonstrate that the proposed architecture has good performances in both speed and area.