Elimination of traditional functional testing of interface timings at Intel

Author

Tripp, Mike ; Mak, T.M. ; Meixner, Anne

Author_Institution

Intel Corp., USA

fYear

2004

fDate

26-28 Oct. 2004

Firstpage

1448

Lastpage

1454

Abstract

This work summarizes the design for test (DFT) circuitry and test methods that enabled Intel to shift away from traditional functional testing of I/O´s. This shift was one of the key enablers for automatic test equipment (ATE) re-use and the move to lower capability (& cost) structural test platforms. Specific examples include circuit implementations from the Pentium^® 4 processor, high volume manufacturing (HVM) data, and evolutionary changes to address key learnings. We close with indications of how this can be extended to cover the next generation high speed serial like interfaces.

Keywords

automatic test equipment; design for testability; high-speed integrated circuits; integrated circuit design; integrated circuit testing; microprocessor chips; peripheral interfaces; ATE; DFT circuitry; HVM data; Intel Pentium^® 4 processor; automatic test equipment; circuit implementations; design for test; functional testing elimination; high speed serial interfaces; high volume manufacturing data; interface timings; lower capability structural test platforms; Automatic test equipment; Automatic testing; Circuit testing; Clocks; Degradation; Jitter; Manufacturing processes; Temperature; Timing; Uncertainty;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2004. Proceedings. ITC 2004. International

Print_ISBN

0-7803-8580-2

Type

conf

DOI

10.1109/TEST.2004.1387457

Filename

1387457