The design of congestion manageable multiprocessor interconnects in a high capacity router

This paper is about multiprocessor interconnects for a high capacity router. In the multiprocessor communication, most transfers are from one port to the other ports or the opposite direction (usually between a main processor and local processors on line cards). Congestion may happen when inter-processor communication packets from local processors are simultaneously heading for a main processor. In order to manage or alleviate the congestion, bandwidth for inter-processor communication should be increased and QoS mechanisms should be introduced in multiprocessor interconnects. This study suggests three ways to build multiprocessor interconnects and discusses them in the view of congestion handling ability and implementation feasibility.