Design for high-speed RS-codec based on Galois-field arithmetics

This work presents the design of a high speed (255, 239) Reed-Solomon (RS) coder and decoder (CODEC) for high-speed application systems, adopting the proposed high-speed GF(2^m) arithmetic elements, such as a standard-basis GF(2^m) multiplier mid inversion circuit. These GF(2^m) arithmetic elements are designed in semi-systolic and parallel processing architecture to improve performance in the sense of speed, complexity, and latency. When using 0.25 μm CMOS technology, we implement the designed (255,239) RS CODEC, operated at clock speed of 580 MHz for worst-case environment, and at throughput rate of 4.64 Gbits/s with 181.717 gates in 654 latency, with a supply voltage of 2.5 V.