Area-efficient video transform for HEVC applications

A hardware design capable of supporting high-efficiency video coding (HEVC) inverse transform (IDCT) is developed for a 32-point transform unit using a single one-dimensional (1D) transform core with two transposed memories to reduce area overhead. The proposed 1D core employs two calculation paths to obtain high throughput and is able to calculate first-dimensional (1st-D) and second-dimensional (2nd-D) transformations simultaneously along two parallel paths. The results from a practical implementation of the chip demonstrate that the proposed design presents the smallest circuit area among existing 2D transform cores.