Arbitration for the segmented bus architecture

We discuss arbitration aspects concerning a segmented bus platform for SOC, at the level of the central arbiter unit. Placed somewhere mid-way between the classical system bus and the network on chip approaches, the segmented bus architecture provides certain performance improvements in comparison with the first, while employing a much simpler communication structure and algorithm than those thought for the second. Our implementation strategy targets an FPGA technology. The result comes as a parameterized arbitration and communication scheme for system on chip designers.