DocumentCode
430271
Title
Design reuse and design for reuse, a case study on HDSL2
Author
Ahonen, Tapani ; Nurmi, Jari
Author_Institution
Tampere Univ. of Technol., Finland
fYear
2004
fDate
16-18 Nov. 2004
Firstpage
129
Lastpage
133
Abstract
Design reuse offers time-to-market reduction through exploitation of previously created components and subsystems. Wide adoption of design reuse lays the foundation for the development of system-level design methodologies. The study described here focused on the design for reuse of an HDSL2 transceiver SoC and its components. The problems faced when trying to reuse old macro components are discussed and the disciplines adopted to ensure reusability of the created intellectual property (IP) are summarized. The disciplines have proven effective, as the Viterbi decoder component was modified for reuse in an asynchronous environment in another university without any support from the original designer.
Keywords
Viterbi decoding; circuit CAD; digital subscriber lines; industrial property; integrated circuit design; logic CAD; system-on-chip; transceivers; HDSL2 transceiver SoC; Viterbi decoder component; asynchronous environment; design for reuse; design reuse; high-speed digital subscriber line generation two; intellectual property reusability; macro components; system-level design methodologies; time-to-market reduction; Computer aided software engineering; DSL; Decoding; Modems; Productivity; System-level design; Time to market; Transceivers; Transmitters; Viterbi algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
System-on-Chip, 2004. Proceedings. 2004 International Symposium on
Print_ISBN
0-7803-8558-6
Type
conf
DOI
10.1109/ISSOC.2004.1411165
Filename
1411165
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