A fully integrated 5.2 GHz CMOS inductively degenerated low noise amplifier

Author

Wang, Ruey-Lue ; Chen, Huang Wei ; Liou, Jim-Shiuan ; Tu, Chih-Ho

Author_Institution

Dept. of Microelectron. Eng., Nat. Kaohsiung Marine Univ., Taiwan

Volume

1

fYear

2004

fDate

6-9 Dec. 2004

Firstpage

285

Abstract

This work presents a fully integrated 5.2 GHz inductively degenerated low noise amplifier (LNA) design fully integrated in a TSMC 0.25 μm CMOS process. We design a 0.516nH minute inductor as a source inductor by the EM analysis of the ADS. The designed LNA consumes 11.9 mW DC power. At 5.2 GHz, this fabricated LNA has noise figure (NF) of 3.54 dB, with input return loss of -15.29 dB, output return loss of -18.1 dB, and voltage gain of 11.78 dB. The simulated and measured results are approximate.

Keywords

CMOS analogue integrated circuits; MMIC amplifiers; integrated circuit design; integrated circuit noise; 0.25 micron; 11.78 dB; 11.9 mW; 3.54 dB; 5.2 GHz; CMOS inductively degenerated low noise amplifier; EM analysis; LNA design; TSMC CMOS process; input return loss; output return loss; CMOS technology; Circuit noise; Cities and towns; Inductors; Low-noise amplifiers; Noise figure; Noise measurement; Radio frequency; Radiofrequency integrated circuits; Receivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-8660-4

Type

conf

DOI

10.1109/APCCAS.2004.1412750

Filename

1412750