An ultra low-power output feedback flip-flop

In this paper, we proposed a new low-power output feedback single edge-triggered flip-flop (FBFF) that eliminates unnecessary internal transitions at the precharge node. As a result, the proposed FBFF is able to achieve substantial power reduction with no impact on its latency. The comparison of simulation results had indicated a maximum power saving of 87.9% during low input activities and an enhanced power-delay-product (in terms of the clock-to-output delay) of 8%-50%