Design of a dual-band 5/2.4 GHz CMOS VCO for 802.11 A/B/G WLAN transceivers

Author

Fard, Ali ; Johnson, Tord ; Åberg, Denny

Author_Institution

Dept. of Electron., Malardalen Univ., Vasteras

Volume

1

fYear

2004

fDate

6-9 Dec. 2004

Firstpage

429

Abstract

A dual-band CMOS VCO with a divide-by-two circuit, operating between 4.7-6.2/2.35-3.1 GHz is demonstrated in a 0.35mum process. The VCO phase noise is reduced by matching the transconductance and impedance of the active devices. By using a divide-by-two stage quadrature signals for the 802.11 b/g standards are obtained. The VCO is optimized for low phase noise and small amplitude variations across the tuning range. The phase noise levels are less than -116.5 and -126 dBc/Hz at 1 MHz offset in the upper and lower frequency band respectively

Keywords

CMOS integrated circuits; circuit tuning; integrated circuit design; phase noise; transceivers; voltage-controlled oscillators; wireless LAN; 0.35 micron; 2.35 to 3.1 GHz; 4.7 to 6.2 GHz; WLAN transceivers; divide-by-two circuit; dual-band CMOS VCO; impedance; noise level; phase noise; transconductance; tuning range; voltage controlled oscillator; CMOS process; Circuits; Dual band; Impedance; Phase noise; Transceivers; Transconductance; Tuning; Voltage-controlled oscillators; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on

Conference_Location

Tainan

Print_ISBN

0-7803-8660-4

Type

conf

DOI

10.1109/APCCAS.2004.1412788

Filename

1412788