An optimization approach for SoC FSM verification

Verification is a bottleneck in IC design, and how to do FSM verification is the main part of the problem. A new approach based on digraph theory and mathematical programming, whose target is to verify all the state transitions in the optimized time, is presented in This work. The FSM verification path can be generated automatically by this approach and this method has been applied in the C*SOC verification environment, and the experimental result shows the method can accelerate the verification process efficiently.